1. Technical Field
This invention generally relates to microelectronics, and more particularly, to a method of producing strained crystalline semiconductor-based microelectronic and/or optical integrated and discrete devices.
2. Background of the Invention
Crystalline semiconductors have proven to be increasingly useful. Types of crystalline semiconductor-based microelectronic devices are given here to include integrated circuits and discrete devices of all types including; uni-polar transistors, bi-polar transistors, radiation emitting devices, photo-sensitive devices, lasers, photonic devices and the crystalline semiconductor material itself.
Integrated circuits, for example, are produced on silicon (Si) wafers. It has been found that introducing strain into the integrated circuit has beneficial properties, e.g., increased conductance. This is increasingly important as the limits of the semiconductor material and current fabricating processes are reached.
At present all high performance tensile strained-silicon devices are strained bi-axially via expensive, highly technical heterostructure fabrication. Strain is introduced in a silicon layer by incorporating atoms of larger atomic volume into the silicon lattice, such as germanium (Ge), then epitaxially growing a strained-silicon layer on top. The Ge/Si layers must be relaxed before the Si is pseudomorphically deposited. The deposited silicon layer is bi-axially strained as a result of lattice mismatch. The entire process is expensive as strain is induced prior to processing and subsequent device fabrication is entirely non-standard. This research is device-level research only.
With regard to integrated circuit fabrication, metal oxide semiconductor field effect transistors (MOSFETs) form the basis of complementary metal oxide semiconductor (CMOS) circuits, which are by far the most common integrated circuits. As integrated circuits, such as microprocessors, evolve, faster operating performance is required. It is preferable, for speed and power considerations, for the chip to be as small as possible, decreasing dimensions is termed scaling. As CMOS dimensions decrease to deep submicron channel lengths ( less than 0.2 microns), subtle short channel effects such as source/drain parasitic resistances and velocity saturation of carriers in the channel, become more significant. Other types of devices also benefit from the introduction of strain within the semiconductor device, e.g., bipolar transistors.
The present invention is aimed at one or more of the problems identified above.
In a first aspect of the present invention, a method of producing a strained crystalline semiconductor microelectronic device is provided. The microelectronic device is formed within a membrane. The method includes the steps of straining a membrane along at least one axis and bonding the membrane to a base substrate.
In a second aspect of the present invention, a method for producing a strained crystalline microelectronic device is provided. The method includes the steps of producing a microelectronic device in the form of a membrane, straining the membrane along at least one axis, and bonding the membrane to a base substrate.
In a third aspect of the present invention, a method of producing strained crystalline microelectronic devices is provided. A plurality of crystalline microelectronic devices is integrally formed in a membrane. The method includes the steps of producing the membrane, straining the membrane along at least one axis, mounting and bonding the membrane on a base substrate, and dicing the membrane to separate the strained crystalline microelectronic devices.
In a fourth aspect of the present invention, a method of producing a strained crystalline microelectronic device is provided. A microelectronic device is formed in a membrane. The method includes the steps of bonding a base substrate to a first side of the membrane, bonding an upper substrate to a second side of the membrane, and applying sheer strain to the membrane by applying force to the base and upper substrate.